Synplicity's Certify Software Eases ASIC Prototyping with Support for Xilinx Virtex-5 FPGAs
Synplicity's Certify Software Eases ASIC Prototyping With Support for Xilinx Virtex-5 FPGAs
Software Extends Automation of ASIC Prototyping Flow; Enhances Quick Partitioning Technology
Sunnyvale, CA, January 29, 2007 * * * Synplicity, Inc. (Nasdaq: SYNP), a leading supplier of software for the design and verification of semiconductors, today announced its Certify® ASIC RTL prototyping software delivers optimal support for the Xilinx Virtex-5 family of 65-nanometer FPGAs. The Certify software is the leading product for ASIC prototyping using multiple FPGAs. By combining multi-chip partitioning with best-in-class FPGA synthesis, the Certify tool allows designers to take full advantage of the speed, versatility and ultra-high capacity of Xilinx Virtex-5 devices for FPGA-based prototyping. Designers who use the Virtex-5 devices in combination with the Certify software should be able to fit more of their ASIC design onto fewer FPGA devices making prototyping quicker, easier and less expensive.
Using the latest version of the Certify product, designers can expect shorter prototype development times and improved prototype performance due in part to enhancements to two of the tool's most powerful and unique partitioning features: Quick Partitioning Technology (QPT) and the Certify Pin Multiplexer (CPM). Quick Partitioning Techno-logy performs automatic pin assignments and, following initial manual placement of key logic blocks, automatically completes partitioning of the remaining blocks between FPGAs. The Certify Pin Multiplexer allows I/O pins of the FPGA device to be shared without any changes to RTL code, alleviating one of the biggest problems typically encountered when partitioning a design across multiple FPGAs - running out of I/O pins. With the enhanced CPM feature, algorithms in the Certify software now utilize detailed knowledge of the FPGA's clock network, dramatically increasing the clock speed of the prototype and delivering fast and accurate pin multiplexing implement-tation. In addition to QPT and CPM enhancements, the automated DesignWare Conversion and automated Gated Clock Conversion features allow designers to use the ASIC RTL as is, without requiring manual changes.
"Based on feedback from our customers and prototyping board partners, we believe there is dramatic growth in the use of FPGA-based prototyping for ASIC verification," said John Gallagher, director of outbound marketing at Synplicity. "Our Certify soft-ware offers a comprehensive ASIC prototyping solution which eases the prototyping process, saving valuable design time and engineering resources. When used with the ultra high-performance Xilinx Virtex-5 devices, we believe designers using the Certify software will implement ASIC prototypes at higher speeds in less time."
Pricing and Availability
The latest version of the Certify software is available to customers starting in February 2007. Pricing for the Certify software starts at $45,000 (U.S.) for a one-year time-based license. Current Certify customers on maintenance will be upgraded at no additional cost. For information about Synplicity's Certify software, contact a Synplicity sales representative or visit http://www.synplicity.com
About the Certify Software
The Certify software is a proven methodology for verifying ASICs using FPGAs. Since its introduction in 1999 the software has been adopted by large and small companies alike and is currently in use at over 100 sites worldwide. It is believed to be the industry's first register transfer level (RTL) prototyping solution that enables designers to create functional hardware prototypes of their ASIC design at the RTL, prior to ASIC synthesis. Verification at this early stage of design results in a dramatic increase in productivity and enables faster time to market. Synplicity believes that prototypes defined by the Certify product will enable extensive verification, allowing ASIC designers to perform the following tasks at- or near-system speed: hardware/software co-verification; algorithm development and verification; verification of intellectual property, either cores or library elements; system software development and debug-ging; verification of system-level protocol compatibility and early system/product development with FPGAs.
About Synplicity's Partners in Prototyping Program
Many of the world's leading FPGA-based prototyping board vendors have joined Synplicity's Partners in Prototyping (PIP) program to develop flows for their boards using Synplicity's tools. The PIP program is used to identify and qualify design methodologies between Synplicity's prototyping applications and complementary RTL functional prototyping hardware, software and design services.
Members of the program include Altera, AMO GmbH, ARM, The Dini Group, Flexody, GiDEL, HARDI Electronics, Nallatech, ProDesign and SK-Electronics Co.
For more information on Synplicity's Partners in Prototyping go to http://www.synplicity.com/partners/pip/index.html.
Synplicity® Inc. (Nasdaq:SYNP) is a leading supplier of innovative software solutions that enable the rapid and effective design of Programmable Logic Devices (FPGAs, PLDs and CPLDs) that serve a wide range of communications, military/aerospace, consumer, semiconductor, computer, and other electronic systems markets. Synplicity's tools provide outstanding performance, cost and time-to-market benefits by simplifying, improving and automating key design planning, logic synthesis, physical synthesis and verification functions for FPGA, FPGA-based ASIC verification, and DSP designers. Synplicity is the number one supplier of FPGA synthesis solutions and has been rated #1 in customer satisfaction since 2004 in EE Times' Annual FPGA Customer Survey. Synplicity products support industry-standard design languages (VHDL and Verilog) and run on popular platforms. The company operates in over 20 facilities worldwide and is headquartered in Sunnyvale, California. For more information visit http://www.synplicity.com.
This press release contains forward-looking statements including, but not limited to, statements regarding the performance, achievements and benefits of the latest version of the Certify software and the growth in the use of FPGA-based prototyping for ASIC verification. In some cases, you will be able to identify forward-looking statements by terminology such as "may," "will," "should," "expects," "believes" or the negative of these terms or other comparable terminology. These statements are only predictions and involve known and unknown risks, uncertainties and other factors that may cause the actual results to differ materially from the forward-looking statements, including the performance and benefits of Synplicity's software relative to relevant industry methods, the standards, design flaws, design difficulties or other problems with Synplicity's software and the growth and changing technical requirements in the ASIC prototyping market. For additional information and considerations regarding the risks faced by Synplicity, see its annual report on Form 10-K for the year ended December 31, 2005 as filed with the Securities and Exchange Commission, as well as other periodic reports filed with the SEC from time to time, including its quarterly reports on Form 10-Q. Although Synplicity believes that the expectations reflected in the forward-looking statements are reasonable, Synplicity cannot guarantee the future performance or achievements of its software. In addition, neither Synplicity nor any other person assumes responsibility for the accuracy or completeness of these forward-looking statements. Synplicity disclaims any obligation to update information contained in any forward-looking statement.
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