Aldec strengthens Verilog Simulator in Riviera PRO
Press Release 06/2006
Aldec Strengthens Verilog Simulator in Riviera-PRO
Average performance gain of 57% on RTL and 250% on gate level and timing simulations
Henderson, Nevada, October 16, 2006 * * * Aldec, Inc., a pioneer in mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced the release of Riviera-PRO 2006.10 HDL simulator. This release adds the high performance SLP (System Level Platform) technology and is an important milestone for Aldec in Verilog RTL, gate and timing simulation. Customers that currently own Riviera-PRO will see an average performance gain of 57% on their RTL and 250% on gate level and timing simulations over previous releases of the software.
Riviera-PRO adds the ability to use generics (parameters) in instantiations of SystemC modules in VHDL or Verilog code and HDL block instantiations within SystemC code. Visibility of SystemC objects in debugging windows is also improved. Support for Microsoft Visual Studio 8.0 (Windows platform) and newer versions of gcc compilers is available.
Support for SystemVerilog (IEEE Std 1800-2005) and PSL (IEEE Std 1850-2005) is extended in this release of Riviera-PRO. The enhancements should affect both testbenches and design code.
Numerous improvements have been made to the existing functionality of Riviera-PRO and new features requested by users have been implemented in the Waveform Viewer including better zooming and scrolling, more alignment options, easier access to search options and support for new waveform formats.
New and Improved Debugging Features
Users of expression coverage can now better control analyzed hierarchical regions of the design and merge data from different sessions. In addition, new signals can be added to toggle coverage during the simulation session. Finally, Xtrace can be linked with Advance Dataflow, allowing better visualization of distribution of the irregular values.
Open IP Encryption (originally developed by Synplicity) is now available for VHDL code in addition to previously available Verilog code encryption. Several new commands and new arguments of the existing commands are also now supported, and compilation times and memory usage for VHDL and Verilog are significantly reduced.
"Aldec's engineering team has worked extremely hard to upgrade our Verilog simulator to include the new SLP simulation technology. In this release we have seen measurable performance gains at customer sites on ASIC and large FPGA designs at all three levels of verification." commented Dave Rinehart, Vice President Aldec, Inc. "Additional optimizations will be preformed in subsequent releases providing even greater performance gains especially in areas of SystemVerilog (IEEE 1800)."
Riviera 2006.10 is available today in two configurations Riviera-SE and Riviera-PRO, all licenses are floating and support UNIX, Windows® and Linux. The product is sold directly by Aldec, Inc. and its authorized international distributors. Download a copy of Riviera from www.aldec.com.
Riviera, a high-performance verification tool, is based on Aldec's industry-proven VHDL and Verilog mixed-language simulation technology and is used by ASIC and high-density FPGA designers for new generation system-on-chip designs. It supports IEEE VHDL 1076-87/93 and VITAL 2000 in addition to Verilog 1364-2001 and SystemVerilog, Code coverage, Waveform Viewer, Advanced Dataflow, Design Profiler and PLI/VPI and VHPI support.
Aldec, Inc., a 22-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software and hardware for UNIX®, Linux® and Windows® platforms. Aldec is dedicated and responsive to serving its customers' needs with its offices located around the globe. Continuous innovation, superior product quality and a total commitment to customer service comprise the foundation of Aldec's strategic objectives. Additional information about Aldec is available at http://www.aldec.com.
* * *
Riviera is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
Tel: +1-702-990-4400 ext. 205
Tel.: +49-8106-24 72 33